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Si5040
Rev. 1.3 29
6. Transmitter
The Si5040 transmitter includes an XFI-compliant, fixed-equalizer CDR for recovery of clock and data from the XFI
channel (TD inputs), pattern generation and checking function (see “6.3. Clock and Data Recovery (CDR)”),
transmit FIFO, and jitter-attenuating clock multiplier unit.
6.1. Transmitter Loss-of-Signal Alarm (LOS)
The Si5040 transmitter generates a loss-of-signal alarm when the TD input signal fails to meet the selected
programmable condition for Transmit Loss of Signal. The programmable LOS mode is controlled in the TxLosCtrl
register (Register 138). The available modes are Digital Loss of Signal (DLOS) and Signal Quality Monitor (SQM).
The state of LOS is reflected in the LOS bit in the TxLosStatus register (Register 139). LOS may also be configured
to generate an interrupt. The status of the LOS interrupt bit may be read in the TxintStatus register (Register 133).
The status of the various LOS modes is stored in the TxLosStatus register (Register 139).
A DLOS alarm occurs when the bit stream on the TD input contains a run length of ones or zeroes greater than the
value loaded in the TxdLosAssertThresh register (Register 145). dLos will remain asserted until the bit stream
shows activity for a time greater than that loaded in the TxdLOSClearThresh register (Register 146).
An SQM alarm occurs when the TD input signal quality falls below the value loaded in TxSqmThresh
(Register 154). The Signal Quality Monitor measures the magnitude of the horizontal eye opening of the received
signal. The SQM value can be read from the TxsqmValue register (Register 153). An SQM alarm will assert if the
TxsqmEn bit has been set in the TxSqmConfig register (Register 154). SQM hysteresis is set in the
TxsqmDeassertThresh register (Register 155).
The transmitter may be programmed to cause the following events on an LOS condition:
1. Disable (squelch) the transmitter data output (TXDOUT) (Register 156).
2. Generate a clock pattern at the transmit data output (TXDOUT) (Register 156).
6.2. Transmit Equalizer
The TX equalizer is a passive, fixed-gain equalizer based on the inverse response of the XFI channel. The
equalizer attenuates the low-frequency components of the input signal to compensate for the high-frequency
losses through the XFI channel. The overall frequency response through the XFI channel and the equalizer should
be essentially flat.
6.3. Clock and Data Recovery (CDR)
The Si5040 integrates a CDR to recover the clock and data from the signal applied to the TD input. The CDR may
be operated with or without an external reference clock. Reference and referenceless operation is programmed in
the TxCalConfig register (Register 136). If a reference clock is applied, the CDR may be forced to lock to the
reference clock in the event that a loss of signal occurs. This option is programmed in the TxConfig register
(Register 135).
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.3 2
- TABLE OF CONTENTS 3
- Measurement 4
- 2. Electrical Specifications 5
- Table 2. DC Characteristics 6
- 8 Rev. 1.3 8
- = 1.8 V +5/–10%, T 8
- = –40 to 95 C) 8
- 10 Rev. 1.3 10
- Table 7. CMU Timing Modes 12
- Rev. 1.3 13 13
- Table 8. AC Characteristics—I 14
- C Bus Lines (SD, SCK) 14
- 765432 76543210 15
- Read Command Read Data 15
- 16 Rev. 1.3 16
- Rev. 1.3 17 17
- 4. Functional Description 18
- Normalized Output Amplitude 19
- 5.2. Limiting Amplifier 20
- Rev. 1.3 21 21
- 22 Rev. 1.3 22
- 5.5. Receiver Slice Control 23
- 5.7. Reference Clock 24
- Rev. 1.3 25 25
- 26 Rev. 1.3 26
- Rev. 1.3 27 27
- 5.9. Receiver Phase Adjust 28
- 6. Transmitter 29
- 30 Rev. 1.3 30
- Rev. 1.3 31 31
- 32 Rev. 1.3 32
- 7. Loopback Modes 33
- 8. Looptime Mode 33
- 10.1. I 35
- C Interface 35
- 10.2. SPI-Like Interface 36
- 11. Interrupt Functionality 37
- 38 Rev. 1.3 38
- Rev. 1.3 39 39
- 13. Si5040 Register Summary 40
- 44 Rev. 1.3 44
- 46 Rev. 1.3 46
- Rev. 1.3 47 47
- 48 Rev. 1.3 48
- Rev. 1.3 49 49
- 50 Rev. 1.3 50
- 52 Rev. 1.3 52
- Register 10 52
- Rev. 1.3 53 53
- 54 Rev. 1.3 54
- 56 Rev. 1.3 56
- 00 0000 0000 = 0 mV 56
- 11 1111 1111 = 1022 mV 56
- Rev. 1.3 57 57
- Rev. 1.3 59 59
- 60 Rev. 1.3 60
- Note: Default = 10 (decimal) 60
- Note: Default = 15 (decimal) 60
- Rev. 1.3 61 61
- Rev. 1.3 63 63
- Exponent 69
- 70 Rev. 1.3 70
- 72 Rev. 1.3 72
- Rev. 1.3 73 73
- 74 Rev. 1.3 74
- Rev. 1.3 75 75
- 76 Rev. 1.3 76
- Rev. 1.3 77 77
- 78 Rev. 1.3 78
- Rev. 1.3 79 79
- 80 Rev. 1.3 80
- Rev. 1.3 81 81
- 82 Rev. 1.3 82
- Rev. 1.3 83 83
- 84 Rev. 1.3 84
- Rev. 1.3 85 85
- 86 Rev. 1.3 86
- Note: Default = 1 (decimal) 86
- Note: Default = 8 (decimal) 86
- Rev. 1.3 87 87
- Bit D7 D6 D5 D4 D3 D2 D1 D0 87
- Rev. 1.3 89 89
- Rev. 1.3 95 95
- 96 Rev. 1.3 96
- 98 Rev. 1.3 98
- Rev. 1.3 99 99
- 14. Pin Descriptions: Si5040 100
- Rev. 1.3 101 101
- Input/Output 101
- 102 Rev. 1.3 102
- 15. Ordering Guide 103
- 16. Package Outline: Si5040 104
- Rev. 1.3 105 105
- DOCUMENT CHANGE LIST 106
- Revision 0.86 to Revision 1.2 107
- Revision 1.2 to Revision 1.3 107
- CONTACT INFORMATION 108
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