Datacom Systems D56 Especificações Página 48
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Si5040
48 Rev. 1.3
Reset settings = 0000 0000
Register 5. RxintStatus (Sticky Bits)
BitD7D6D5D4D3D2D1D0
Name refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarm
Type R R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6 refLOS Reference Clock LOS Interrupt.
A latched version of the refLOS alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
5LOSLoss of Signal Interrupt.
A latched version of the LOS alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
4LOLLoss of Lock Interrupt.
A latched version of the LOL alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
3fifoErrReceiver FIFO Error Interrupt.
A latched version of the fifoErr alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
2 tpErrAlarm Test Pattern Generator/Checker Alarm Interrupt.
A latched version of the tpErrAlarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
1 tpSyncLos Test Pattern Checker Loss of Sync Interrupt.
A latched version of the tpSyncLos alarm status bit. An interrupt is generated if interrupts
are enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit.
The interrupt may be cleared by writing a zero to this bit position or by disabling inter-
rupts.
0sqmAlarmSignal Quality Monitor Alarm Interrupt.
A latched version of the sqmAlarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.3 2
- TABLE OF CONTENTS 3
- Measurement 4
- 2. Electrical Specifications 5
- Table 2. DC Characteristics 6
- 8 Rev. 1.3 8
- = 1.8 V +5/–10%, T 8
- = –40 to 95 C) 8
- 10 Rev. 1.3 10
- Table 7. CMU Timing Modes 12
- Rev. 1.3 13 13
- Table 8. AC Characteristics—I 14
- C Bus Lines (SD, SCK) 14
- 765432 76543210 15
- Read Command Read Data 15
- 16 Rev. 1.3 16
- Rev. 1.3 17 17
- 4. Functional Description 18
- Normalized Output Amplitude 19
- 5.2. Limiting Amplifier 20
- Rev. 1.3 21 21
- 22 Rev. 1.3 22
- 5.5. Receiver Slice Control 23
- 5.7. Reference Clock 24
- Rev. 1.3 25 25
- 26 Rev. 1.3 26
- Rev. 1.3 27 27
- 5.9. Receiver Phase Adjust 28
- 6. Transmitter 29
- 30 Rev. 1.3 30
- Rev. 1.3 31 31
- 32 Rev. 1.3 32
- 7. Loopback Modes 33
- 8. Looptime Mode 33
- 10.1. I 35
- C Interface 35
- 10.2. SPI-Like Interface 36
- 11. Interrupt Functionality 37
- 38 Rev. 1.3 38
- Rev. 1.3 39 39
- 13. Si5040 Register Summary 40
- 44 Rev. 1.3 44
- 46 Rev. 1.3 46
- Rev. 1.3 47 47
- 48 Rev. 1.3 48
- Rev. 1.3 49 49
- 50 Rev. 1.3 50
- 52 Rev. 1.3 52
- Register 10 52
- Rev. 1.3 53 53
- 54 Rev. 1.3 54
- 56 Rev. 1.3 56
- 00 0000 0000 = 0 mV 56
- 11 1111 1111 = 1022 mV 56
- Rev. 1.3 57 57
- Rev. 1.3 59 59
- 60 Rev. 1.3 60
- Note: Default = 10 (decimal) 60
- Note: Default = 15 (decimal) 60
- Rev. 1.3 61 61
- Rev. 1.3 63 63
- Exponent 69
- 70 Rev. 1.3 70
- 72 Rev. 1.3 72
- Rev. 1.3 73 73
- 74 Rev. 1.3 74
- Rev. 1.3 75 75
- 76 Rev. 1.3 76
- Rev. 1.3 77 77
- 78 Rev. 1.3 78
- Rev. 1.3 79 79
- 80 Rev. 1.3 80
- Rev. 1.3 81 81
- 82 Rev. 1.3 82
- Rev. 1.3 83 83
- 84 Rev. 1.3 84
- Rev. 1.3 85 85
- 86 Rev. 1.3 86
- Note: Default = 1 (decimal) 86
- Note: Default = 8 (decimal) 86
- Rev. 1.3 87 87
- Bit D7 D6 D5 D4 D3 D2 D1 D0 87
- Rev. 1.3 89 89
- Rev. 1.3 95 95
- 96 Rev. 1.3 96
- 98 Rev. 1.3 98
- Rev. 1.3 99 99
- 14. Pin Descriptions: Si5040 100
- Rev. 1.3 101 101
- Input/Output 101
- 102 Rev. 1.3 102
- 15. Ordering Guide 103
- 16. Package Outline: Si5040 104
- Rev. 1.3 105 105
- DOCUMENT CHANGE LIST 106
- Revision 0.86 to Revision 1.2 107
- Revision 1.2 to Revision 1.3 107
- CONTACT INFORMATION 108
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