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Si5040
36 Rev. 1.3
10.2. SPI-Like Interface
When configured in SPI-like control mode (pin SPSEL tied high), the control interface to the Si5040 is a 3-wire
interface modeled close to commonly-available microcontrollers and bidirectional serial peripheral devices. The
interface consists of a clock input (SCK), slave select input (SS), and serial data input/output (SD). The SD pin may
be configured as a CMOS output or as an open drain output using Register 2, bit 4.
Data is transferred one byte at a time, with each register access consisting of a pair of byte transfers. Figure 7 and
Figure 8 on page 15 illustrate read and write/set address operations on the SPI bus, and Table 9 on page 14 gives
the timing requirements for the interface. Table 12 shows the SPI command format.
The first byte of the pair is the instruction byte. The "Set Address" command writes the 8-bit address value that will
be used for the subsequent read or write.
The "Write" command writes data into the device based on the address previously established, and the "Write/
Address Increment" command writes data into the device and automatically increments the register address for
use on the subsequent command. The "Read" command reads one byte of data from the device, and the
"Read/Address Increment" reads one byte and increments the register address automatically.
The second byte of the pair is the address or data byte. As shown in Figure 7 and Figure 8 on page 15, SS should
be held low during the entire two byte transfer. Raising SS resets the internal state machine; so, SS must be raised
between each two byte transfers to guarantee that the state machine will be reinitialized.
During a read operation, the SD becomes active on the falling edge of SCK, and the 8-bit contents of the register
are driven out MSB first. The SD is high-impedance on the rising edge of SS. During write operations, data is
driven into the Si5040 via the SD pin MSB first. Data always transitions with the falling edge of the clock and is
latched on the rising edge.
The clock should return to a logic high when no transfer is in progress. The Si5040 SPI-like interface supports
continuous clocking operation where SS is used to gate two byte transfers.
Table 12. SPI-Like Command Format
Instruction Address/Dat
00000000—Set Address AAAAAAAA
01000000—Write DDDDDDDD
01100000—Write/Address Increment DDDDDDDD
10000000—Read DDDDDDDD
10100000—Read/Address Increment DDDDDDDD
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.3 2
- TABLE OF CONTENTS 3
- Measurement 4
- 2. Electrical Specifications 5
- Table 2. DC Characteristics 6
- 8 Rev. 1.3 8
- = 1.8 V +5/–10%, T 8
- = –40 to 95 C) 8
- 10 Rev. 1.3 10
- Table 7. CMU Timing Modes 12
- Rev. 1.3 13 13
- Table 8. AC Characteristics—I 14
- C Bus Lines (SD, SCK) 14
- 765432 76543210 15
- Read Command Read Data 15
- 16 Rev. 1.3 16
- Rev. 1.3 17 17
- 4. Functional Description 18
- Normalized Output Amplitude 19
- 5.2. Limiting Amplifier 20
- Rev. 1.3 21 21
- 22 Rev. 1.3 22
- 5.5. Receiver Slice Control 23
- 5.7. Reference Clock 24
- Rev. 1.3 25 25
- 26 Rev. 1.3 26
- Rev. 1.3 27 27
- 5.9. Receiver Phase Adjust 28
- 6. Transmitter 29
- 30 Rev. 1.3 30
- Rev. 1.3 31 31
- 32 Rev. 1.3 32
- 7. Loopback Modes 33
- 8. Looptime Mode 33
- 10.1. I 35
- C Interface 35
- 10.2. SPI-Like Interface 36
- 11. Interrupt Functionality 37
- 38 Rev. 1.3 38
- Rev. 1.3 39 39
- 13. Si5040 Register Summary 40
- 44 Rev. 1.3 44
- 46 Rev. 1.3 46
- Rev. 1.3 47 47
- 48 Rev. 1.3 48
- Rev. 1.3 49 49
- 50 Rev. 1.3 50
- 52 Rev. 1.3 52
- Register 10 52
- Rev. 1.3 53 53
- 54 Rev. 1.3 54
- 56 Rev. 1.3 56
- 00 0000 0000 = 0 mV 56
- 11 1111 1111 = 1022 mV 56
- Rev. 1.3 57 57
- Rev. 1.3 59 59
- 60 Rev. 1.3 60
- Note: Default = 10 (decimal) 60
- Note: Default = 15 (decimal) 60
- Rev. 1.3 61 61
- Rev. 1.3 63 63
- Exponent 69
- 70 Rev. 1.3 70
- 72 Rev. 1.3 72
- Rev. 1.3 73 73
- 74 Rev. 1.3 74
- Rev. 1.3 75 75
- 76 Rev. 1.3 76
- Rev. 1.3 77 77
- 78 Rev. 1.3 78
- Rev. 1.3 79 79
- 80 Rev. 1.3 80
- Rev. 1.3 81 81
- 82 Rev. 1.3 82
- Rev. 1.3 83 83
- 84 Rev. 1.3 84
- Rev. 1.3 85 85
- 86 Rev. 1.3 86
- Note: Default = 1 (decimal) 86
- Note: Default = 8 (decimal) 86
- Rev. 1.3 87 87
- Bit D7 D6 D5 D4 D3 D2 D1 D0 87
- Rev. 1.3 89 89
- Rev. 1.3 95 95
- 96 Rev. 1.3 96
- 98 Rev. 1.3 98
- Rev. 1.3 99 99
- 14. Pin Descriptions: Si5040 100
- Rev. 1.3 101 101
- Input/Output 101
- 102 Rev. 1.3 102
- 15. Ordering Guide 103
- 16. Package Outline: Si5040 104
- Rev. 1.3 105 105
- DOCUMENT CHANGE LIST 106
- Revision 0.86 to Revision 1.2 107
- Revision 1.2 to Revision 1.3 107
- CONTACT INFORMATION 108
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